FIG. 5 is a block diagram showing a prior art amplifier that amplifies a high-frequency wave of more than one GHz. In FIG. 5, reference numeral 10 designates an FET as an active element. A source of the FET 10 is grounded. An input terminal 11 is connected to a gate of the FET 10 through an input matching circuit 30. An output terminal 18 is connected to a drain of the FET 10 through an output matching circuit 40. A signal which is input to the gate is amplified and output from the drain side. In the input matching circuit 30, an input end of a high frequency transmission line 12a is connected to the input terminal 11, a high frequency transmission line 12b and a capacitor 15 are serially connected between the gate of the FET 10 and the ground, and a gate bias terminal 13, which is an output terminal of a gate bias setting circuit 14, is connected to the junction of the high frequency transmission line 12b and the capacitor 15. In the output matching circuit 40, an output end of a high frequency transmission line 16a is connected to the output terminal 18, a high frequency transmission line 16b and a capacitor 17 are serially connected between the drain of the FET 10 and the ground, and a drain bias terminal 20, which is an output terminal of a drain bias setting circuit 19, is connected to the junction of the high frequency transmission line 16b and the capacitor 17. In addition, an external circuit, comprising a load 22 and a DC blocking capacitor 21 connected in series, is connected to the output terminal 18. An external circuit comprising a high frequency signal generating power supply, a load, and the like (not shown) is connected to the input terminal 11.
FIG. 7 is a block diagram showing a circuit structure of the gate bias setting circuit 14 in the input matching circuit 30 (or the drain bias setting circuit 19 in the output matching circuit 40). The gate bias setting circuit 14 (or the drain bias setting circuit 19) comprises a power distributor 24 that extracts out a part of an input signal power applied to the input terminal 11, a power detector 25 that detects the power taken out by the power distributor 24, and a voltage generator 23 that outputs a control applied to the gate bias terminal 13 (drain bias terminal 20) in accordance with the detected power.
A description is given of the operation.
The input impedance matching circuit 30 is provided to match an input impedance of the FET 10 with an impedance of the external circuit (not shown) connected to the gate input of the FET 10 through the input terminal 11. The external circuit comprises the high frequency signal generating power supply, the load, and the like (not shown). Similarly, the output impedance matching circuit 40 is provided to match an output impedance of the FET 10 with an impedance of the external circuit connected to the drain output of the FET 10 through the output terminal 18. When a high frequency signal generated in the high frequency signal generating power supply in the external circuit is input to the input terminal 11, the high frequency signal is amplified by the FET 10 and output from the output terminal 18.
FIGS. 6(a) and 6(b) are diagrams showing operating characteristics of the amplifier of FIG. 5, in which FIG. 6(a) shows an I-V characteristic of the drain of the FET 10 and FIG. 6(b) shows an input-output power characteristic of the FET 10. The operation of the amplifier of FIG. 5 will be described in more detail with reference to FIGS. 6(a) and 6(b).
In FIG. 6(a), where the gate bias and the drain bias are controlled so that a bias point may be point a0 in FIG. 6(a) and a high frequency signal is amplified by a class "B" operation, an output signal after being amplified, i.e., a signal having a drain current and a drain voltage varies along a load curve a1-a0-a2 shown in FIG. 6(a), in accordance with the amplitude of the high frequency signal which is input to the gate (input power. More specifically, when the input power of the high frequency signal which is input to the gate is small, the drain current and the drain voltage move on the load curve in the vicinity of point a0. When the input power increases, the output power which is output from the drain is saturated because the drain current and the drain voltage only take values on the load curve a1-a0-a2 because of the characteristics of the FET. Similarly, when the gate bias and the drain bias are controlled to vary the bias point to points b0 and c0 in FIG. 6(a), the drain current and the drain voltage vary along load curves b1-b0-b2 and c1-c0-c2, which correspond to the bias points b0 and c0, respectively, in accordance with the amplitude of high frequency signal which is input to the gate. When the input power increases, the output power which is output from the drain is saturated in the same manner as described above. FIG. 6(b) shows a relation between the input power of the high frequency signal which is input to the gate of the FET and the output power of the output signal which is output from the drain of the FET. In FIG. 6(b), curves a, b, and c are input-output power characteristic curves corresponding to the bias points a0, b0, and c0, respectively.
Generally, in order to achieve a highly-efficient operation in an amplifier, it is desirable that the output power is output in the saturated state of the amplifier. In the conventional amplifier shown in FIG. 5, a highly-efficient operation is achieved by controlling the gate bias and the drain bias of the FET 10 by the gate bias setting circuit 14 and the drain bias setting circuit 19, respectively, so as to vary the bias point in accordance with the input power of the input signal. More specifically, a part of the high frequency signal power which is input to the input terminal 11 is taken out by the power distributor 24 included in the drain bias setting circuit 19 (or the gate bias setting circuit 14). Then, the power taken out by the power distributor 24 is detected by the power detector 25, and a prescribed voltage is generated in the voltage generator 23 and applied to the drain bias terminal 20 (or the gate bias terminal 13) in accordance with the power detected by the power detector 25. In this way, the gate bias and the drain bias of the FET 10 are controlled so that the bias point may always take the points a0, b0, and c0, at which the output power is in the saturated state of the amplifier, in accordance with the detected input power Pia, Pib, Pic, respectively, as shown in FIG. 6(b). As the result, output powers Poa, Pob, and Poc corresponding to the input powers Pia, Pib, and Pic are obtained in their saturated state, respectively. In addition, as shown by the dotted line in FIG. 6(b), the amplifier is controlled while maintaining the linearity of the output power to the input power.
In the conventional amplifier, however, when the gate bias and the drain bias of the FET 10 are controlled by the gate bias setting circuit 14 and the drain bias setting circuit 19, respectively, in accordance with the input power, the control voltage generated from the drain bias setting circuit 19 must be large because when a large current flows into the drain, the drain voltage is relatively large, or the like. As the result, the circuit structure of the voltage generator 23 included in the drain bias setting circuit 19 is complicated.
In addition, if the drain bias of the FET 10 varies to a significant degree, matching by the output matching circuit 40 changes, adversely affecting the characteristics of the amplifier.